1. Field of the Invention
The present invention relates to dual-port static random access memories (SRAMs), and, more particularly, to a dual-port subthreshold SRAM for operation in a first-in first-out (FIFO) memory system.
2. Description of Related Art
In the semiconductor industry, a single chip system has been developed with a miniaturized size. Particularly, in the biomedical electronic industry, an embedded memory is part of a single chip system, and a static random access memory (SRAM) is widely used for storing and transmitting data.
For an integrated circuit (IC) design in the biomedical electronic industry, fast operation speed is not essential, but long operation without consuming much power is critical. Ultra-low power consumption is achieved by subthreshold operation voltage. However, it needs to consider process variation, voltage variation and temperature variation in a nanometer process. Further, the conventional SRAM has severe diminished the static noise margin (SNM), which adversely affects minor signals.
Therefore, more stable and reliable SRAMs are required for the modern integrated circuits, such that dual-port SRAMs are developed. Referring to FIG. 1, a conventional dual-port SRAM is provided. As shown in FIG. 1, a dual-port SRAM 100 includes cross-coupled inverters 102, 104, a pair of write transistors 108, 112, and a pair of read transistors 106, 110. The cross-coupled inverters 102, 104 are disposed as a memory component at an intermediate region of the dual-port SRAM 100. The write transistor 108 is connected between a write bit line 118 and the memory component via a source/drain of the write transistor 108, and the write transistor 112 is connected between the memory component and a write bit line 120 via a source/drain thereof. The read transistor 106 is connected between the memory component and a read bit line 122 via a source/drain thereof, and the read transistor 110 is connected between the memory component and a read bit line 124 via a source/drain thereof.
However, the SNM becomes smaller due to the diminished signal and the process variation of the dual-port SRAM 100, such that the dual-port SRAM cannot operate at the subthreshold region. In addition, due to the miniaturization of nano-technology and voltage power, the write margin of the dual-port SRAM 100 becomes smaller, and thus additional control circuits are needed for enhancing writing capability. Due to consuming power and increasing the chip area, the additional control circuits are not suitable for FIFO memory systems, which are in long operation.
Accordingly, it is an urgent need to develop SRAMs for long operation at ultra-low voltage, increasing stability, decreasing SNM influence and operation at subthreshold voltage.